Method and device for the formation of clock pulses in a bus system having at least one station, bus system and station

ABSTRACT

A method for forming clock pulses of a second clock cycle (AT, TT) from clock pulses of a specified first clock cycle (ET) in a bus system having at least one user, a first number (E) of the clock pulses of the first clock cycle being determined or specified in a specifiable time interval and a second number (A) of the clock pulses of the second clock cycle being determined or specified in the specifiable time interval, in which an intermediate value (R) of the number of clock pulses is specified in the specifiable time interval, and the intermediate value (R) is compared to a value (C) which is formed from the first number (E) of clock pulses and the second number (A) of clock pulses and from the comparison a truth value (TRUE, FALSE) is yielded, and a clock pulse of the second clock cycle (AT, TT) is generated as a function of the truth value (TRUE, FALSE).

FIELD OF INVENTION

The present invention relates to a method and a device for forming clockpulses in a bus system having at least one user, as well as to a bussystem and a user of the bus system.

BACKGROUND INFORMATION

The networking of control units, sensor systems and actuator systemswith the aid of a communications system, that is, a bus system, hasincreased in recent years in the construction of modern motor vehiclesand in machine construction, especially in the field of machine toolsand in automation. In this context, synergies from the distribution offunctions to several control units can be achieved. These are calleddistributed systems. The communication between various users of suchdistributed systems is occurring more and more via a bus or a bussystem. The communications traffic on the bus system, access andreception mechanisms, as well as error handling are governed via aprotocol.

In the automotive field, an established protocol is the CAN (controllerarea network). This is an event-driven protocol, i.e. protocolactivities such as sending a message are initiated by events which havetheir origin outside the communications system itself. Unique access tothe communications system or bus system is solved by a priority-basedbit arbitration. The presupposition for this is that a unique priorityis assigned to each message. The CAN protocol is very flexible. Whenusing it, the addition of additional nodes and messages is possiblewithout a problem, as long as there are still free priorities (messageidentifiers).

An alternative approach to such an event-controlled, spontaneouscommunication is the purely time-controlled approach. All communicationsactivities on the bus are strictly periodic. Protocol activities such assending a message are triggered only by progress in time valid for theentire bus system. Access to the medium is based on the apportionment oftime periods during which a user has an exclusive transmission right.Such a protocol is comparatively inflexible. Adding new nodes ispossible when the respective time periods were left free ahead of time.This circumstance makes it necessary already to fix the message sequencebefore initial operation. Thus, a timetable is drawn up which has tomeet the demands of the message requirements with respect to rate ofrepetition, redundancy, deadlines, etc. The positioning of the messageswithin the transmission periods must be matched to the applicationswhich produce the message contents, in order to hold the latency betweenapplication and point of transmission time to a minimum. If thismatching does not take place, the advantage of the time-controlledtransmission (minimal latent jitter when sending the message on the bus)is lost. Thus, stringent requirements are placed on the planning tools.

The attempt at an approach, as described in German Patent ApplicationsNos. 100 00 302, 100 00 303, 100 00 304 and 100 00 305, of thetime-controlled CAN, of the so-called TTCAN (time-triggered controllerarea network) satisfies the requirements outlined above fortime-controlled communications, as well as the requirements for acertain degree of flexibility. TTCAN fulfills this by setting up thebasic cycle into so-called exclusive time windows for periodic messagesof certain communications users and into so-called arbitrating timewindows for the spontaneous messages of several communications users.

Besides the bus systems mentioned, a plurality of bus or communicationssystems for connecting users in distributed systems is available.Subsequently, a starting print is from a TTCAN network as the bus systemhaving at least one user, where this should not be understood asrestrictive with respect to the later subject matter of the presentinvention. Rather, the subject matter of the exemplary embodiments ofthe present invention described herein may be used also for furthercomparable bus systems for forming a pulse or clock pulse or pulsedivision.

In this context, for example, in networked control units in automation,in motor vehicles and in other fields of application, a uniform clockpulse must be derived from the various internal, local clock pulses ofthe users, especially of the control units for the communicationsnetwork, that is, the bus system. Likewise, in the networked controlunits named, an internal, local clock cycle of each user must bederivable, for instance as working clock cycle, from one clock cycletransmitted via the bus system or the communications network.

Customary pulse scalers allow for deriving a slower output clock cyclefrom an input clock cycle, the clock cycle period of the output clockcycle being an integral multiple of the clock cycle period of the inputclock cycle.

SUMMARY OF THE INVENTION

Consequently, the subject matter of the present invention provides amethod, a device or a corresponding bus system and a corresponding user,whereby, using pulse scaling, a slower output clock cycle may beproduced from an input clock cycle, the clock cycle period of the outputclock cycle not only being able to be an integral multiple of the clockcycle period of the input clock cycle, but on average also a fractionalrational multiple.

The subject matter of the present invention provides a method, as wellas a device and a corresponding bus system, as well as a user of the bussystem, for forming pulses of a second clock pulse from pulses of aspecified first clock pulse, a first number of pulses of the first clockpulse being ascertained in a specifiable time interval or beingspecified, and a second number of the pulses of the second clock pulsebeing ascertained or specified in the specified time interval;advantageously, an intermediate value of the number of pulses beingspecified in the specifiable time interval, and the intermediate valuebeing compared to a value which is formed from the first number ofpulses and the second number of pulses, and a truth value being derivedfrom the comparison; as a function of the truth value, a clock pulse ofthe second clock cycle being produced.

According to the exemplary embodiment and/or method of the presentinvention, a pulse scaling or a formation of a clock cycle is therebyachieved so that not only an integral, but on average also a fractionalrational multiple of the clock cycle period of the input clock cycle, orrather, the first clock cycle, may be achieved.

In one embodiment, advantageously, besides the intermediate value, ascaling intermediate value is specified, which is compared to aspecified scaling value, and an additional truth value comes about fromthe comparison with the scaling value, a clock pulse of a third clockcycle being producible from the clock pulse of the second clock cycle,as a function of the additional truth value.

This allows for obtaining a finer resolution of the output clock cycleperiod, that is, the clock cycle period of the second and/or third clockcycle than in the known methods.

Furthermore, it is of advantage that, by the measures described herein,a more accurate setting of the clock cycle to be formed comes about,especially of the network clock cycle, even when the input clock cycle,in particular the local clock cycles of the users deviate from theirsetpoint values, for instance by temperature change or temperaturedeterioration. The same also applies to the example of a more exactsetting of the local clock cycles of the users, particularly of the atleast one user, from an input clock cycle of the bus system, especiallyof the network clock cycle.

The above-described method steps are expediently run through once as afunction of each clocked pulse of the clock cycle.

Advantageously, the intermediate value is changed differently, as afunction of the comparison and thus as a function of the truth value.

In one embodiment, the production of the clock pulse of the second clockcycle and/or the third clock cycle and the change of the intermediatevalue or the scaling intermediate value is reset by a specifiable numberof clock pulses of the first clock cycle.

In an expedient manner, the value to which the intermediate value iscompared results from the subtraction of the product of the secondnumber of clock pulses, that is the pulses of the second clock cycle,and an integer F of the first number of clock pulses of the first clockcycle in the specifiable time interval.

In particular, in the specific embodiment, a clock pulse of the secondclock cycle and/or the third clock cycle is generated when the conditionis satisfied that the above-named intermediate value is greater than theaforesaid subtraction result.

In another exemplary embodiment, the integer F is limited to values of2^(n), where nεN₀, so that the multiplication of the number of theclockpulses of the second clock cycle by the whole number may bereplaced by a shift of the binary value of the number of clock pulses ofthe second clock cycle by n bits. Thereby, the method can do withoutmultiplication or division, which may require a great deal ofimplementation expenditure.

During generation of the clock pulses of the third clock cycle, theclock pulses of the second clock cycle are advantageously only availablewithin the user itself, but are not output by it.

BRIEF DESCRIPTIONS OF THE DRAWINGS

FIG. 1 shows a network or a bus system having at least one user,especially a TTCAN bus system having at least one arrangement forcarrying out the method according to the present invention.

FIG. 2 shows a flow diagram on pulse cycle formation, in particularpulse scaling, the integer F being selected to be equal to 1, and forcomparison an intermediate value is specified.

FIG. 3 shows a representation of signals of the clock pulses, to explainthe procedures according to the flow diagram in FIG. 2.

FIG. 4 shows a flow diagram corresponding to FIG. 2, where additionally,besides the intermediate value, a scaling intermediate value isspecified, and corresponding second and third clock cycles are generatedfrom the first clock cycle.

FIG. 5 shows a representation of signals of the clock pulses, to explainthe procedures in the flow diagram in FIG. 3.

DETAILED DESCRIPTION

FIG. 1 shows a bus system 113 having a first user 100 and a second user101, which are connected to each other via a communications connection102. In the users, 103 and 108 each shows a bus control module, aso-called bus controller. The two communications interfaces 106 and 111,as connection to communications connection 102 are here shownseparately, but they may also be accommodated in bus controller 103 and108, or their functionality may be assumed by bus controller 103 and108. In users 100 and 101, clock sources 107 and 112 are shown. Buscontrollers 103 and 108 include the pulse scaler, or rather, thefunctionality of pulse scaling, shown by block 104 and block 109. Inthis context, depending on whether adjustment is necessary, the localclock cycle is adjusted to a common clock cycle of bus system 113, or acommon clock cycle of bus system 113 is transmitted to the appropriateuser via communications connection 102. A local time base is optionallypresent, such as a counter module, especially when it comes to TTCAN,which is shown here by 105 and 110.

Since, as was described, both directions of adjustment are possible,from here on, an input clock cycle and an output clock cycle, or ascaled clock cycle or an output scaled clock cycle are referred to. Inparticular, the adjustment of the clock cycle of a timing generatorexternal to the communications connection as supply clock cycle (quartz,voltage-controlled oscillator, etc), especially of the given clocksource 107 and 112 takes place to a common working clock cycle of thebus system via the bus controller. For this, the pulse scaler is used,for example, an integrated circuit, an IC 104 and 109.

The desired time unit ratio is established by the quotient of the numberof input clock cycles in a given, especially large, time interval andthe number of output clock cycles in the same time interval, thesenumbers E and A being integers. Thus, a time unit ratio TUR is given byTUR=E/A  (equation 1)

Consequently, TUR is a rational number. The length of a single outputclock cycle period ATP is always an integral multiple of the length ofthe input clock cycle period, the following equation holding true:((TUR−0.5)*ETP)<ATP<((TUR+0.5)*ETP)  (equation 2)

This means that the length of any two ATP's differs by maximally oneETP. Consequently, on average,ATP=TUR*ETP  (equation 3)holds.

If the output clock cycle period ATP is subdivided more finely, theindividual parts of output pulse period ATP may be of different lengthsby one input clock cycle period ETP. For the possible resolution ofscaling F it is true thatF≦TUR  (equation 4)holds, F being an integer. Fine division F means that an output pulseperiod ATP is subdivided into F parts.

The clock cycle formation, especially the pulse cycle scaling, accordingto the present invention is now based on the idea that the division byA, that is, the time unit ratio TUR, according to equation 1, isreplaced by an algorithm in such a way that for the conditionN*A−E=R≧0  (equation 5)the minimum value of N is able to be calculated. Consequently, thisyields the length of an output clock cycle period ATP as N times theinput clock cycle period ETP.

The remainders R added from one output clock cycle period ATP to thenext, which is shown next in a simple method according to FIG. 2. Inthis context, E and A are integers having a time unit ratioTUR=E/A≧1  (equation 6).

The remainder R, subsequently referred to as intermediate value, is alsoan integer and begins, for example, at 0. The beginning of the method isshown in block 200 of FIG. 2. In block 201, the input clock pulses areevaluated to the extent that, for each input clock pulse, the subsequentprocess runs. Query 202 checks whether intermediate quantity R isgreater than the difference E−A, thus, whether intermediate quantity Ris greater than the difference of the number of input clock cycles minusthe number of output clock cycles.(R>E−A)  (equation 7)

If this is the case, block 204 is reached, in which, on the one hand, inblock 205 a new intermediate value R is generated or intermediate valueR is changed, and in block 206 a clock pulse of output clock cycle AT isgenerated.

According to the equationR:=R+A−E  (equation 8)intermediate value R is changed. In block 206 an output clock pulse isnow generated. Consequently, for each clock pulse of input clock cycleET a clock pulse of output clock cycle AT is generated, provided thecondition as in equation 7 (R>E−A) is satisfied. If this condition isnot satisfied, the system reaches block 203 from block 202, where therealso takes place an adjustment or change of intermediate value R, inthatR:=R+A  (equation 9)is calculated. From block 204, after the generation of the clock pulseof output clock cycle AT and the change of intermediate quantity Raccording to block 205 or from the different change of intermediatequantity R in block 203, the system reaches block 207, in which isdecided whether the method is to be carried further or the clock cycleadjustment is to be ended. If this is the case, the system reaches block208, the end of the method, or in the other case, it goes back to block201, where the renewed clock pulse of input clock cycle ET is evaluated.In this context, the termination condition after query 207 is optional,and does not have to be included.

According to the exemplary embodiment and/or method of the presentinvention, there are other, equivalent algorithms or methods in which acorresponding clock cycle formation or pulse scaling is achieved, forinstance by, instead of increasing R by A until an output pulsecondition is satisfied, the intermediate value R is reduced until afurther query condition is satisfied. All these equivalent algorithmsaccording to the present invention have the following scheme in common:

-   -   During the application, there is a process which runs once at        each clock pulse of input clock cycle ET (evaluation block 201).    -   This process is able to generate a clock pulse of output clock        cycle AT (corresponding to block 204 and 206).    -   The clock pulse of output clock cycle AT is generated when the        comparison of intermediate value R to an easily calculable fixed        value determined from E and A yields a certain truth value.        Thus, in the previous example, a truth value TRUE is yielded        from block 202 upon satisfaction of the condition R>E−A        according to equation 7, which results in a first change of        intermediate value R according to block 205 and the initiation        of a clock pulse of output clock cycle AT according to block        206. In the case of a second truth value FALSE, i.e. when the        condition R>E−A according to equation 7 is not satisfied,        intermediate value R is adjusted in a different manner according        to block 203, and no clock pulse of the output clock cycle is        generated.    -   Consequently, if a clock pulse of output clock cycle AT is        generated, a certain first manipulation M1 is undertaken with R,        for instance, an addition or subtraction of a value that is        calculable from A and E.    -   If no clock pulse of output clock cycle AT is generated, a        certain other manipulation M2 is undertaken with R, just as        here, for example, the addition of A.

As a variant of this method or approach, the step of generating theclock pulse of the output clock cycle and manipulation M1 ofintermediate value R may be split up in such a way that the output ofthe clock pulse of output clock cycle AT and manipulation M1 ofintermediate value R do not occur simultaneously, but are offset by aspecifiable number, in particular, a fixed number of clock pulses ofinput clock cycle ET.

A further optional variant is that the certain further manipulation M2with intermediate value R is always executed, and in the previous step,that is, in case a clock pulse of output clock cycle AT is generated,only the difference with respect to manipulation M1 compared to thismanipulation M2 is still set in addition.

A concrete example to illustrate the method just described is shown inFIG. 3. This shows the number of clock pulses of input clock cycle ET, Eat 7, and the number of clock pulses of output clock cycle AT, A in thesame time interval at 3. Consequently, this yields a difference of E−Aequals 4. As was mentioned before in exemplary fashion, intermediatevalue R starts, in particular, at 0. The first clock pulse of inputclock cycle is not shown, because it is only valid for the startingvalues. Thus, for this first input clock cycle, R<4 applies, wherebytruth value FALSE is generated, and in block 203, with R:=R+A=3,intermediate value R has 3 allocated to it. At the next clock pulse ofinput clock cycle ET at T1, R thus=3. Once again, R<4. The truth valueFALSE is again generated, and in block 203 A=3 is added. That makes R=6.At the next clock pulse at time T2, thus R=6, so that R>4, whereby truthvalue TRUE is generated. In block 205 the new value for R is formed.With R:=R+A−E=2 and block 206 an output clock pulse is then generated.At time T3, consequently, R=2, and no output clock pulse is generated.But in block 203 the new value is determined by truth value FALSE, whichyields R=5. Thus, at point T4, for R=5 a clock pulse of output clockcycle AT is generated anew. At point T5 and T6, via block 203 andcorresponding to truth values FALSE, the new R values are determinedwith R=1 at T5 and R=4 at T6. The next output clock cycle is thengenerated for R=7 with R>4 at point T7. Beginning at T8, the methodsteps repeat beginning with R=3, as shown.

In this example, as points in time T1 the rising sides of the clockpulses of the input clock cycle have been picked. This is not essential.Equal results may be carried out for the lowering sides or otherrecognizable states of the clock pulses of the input clock cycle.Consequently, at points T2, T4 and T7 clock pulses of the output clockcycle are generated. Consequently, a fractional rational time unit ratiomay be shown here, such as TUR= 7/3=2⅓, which then simply means two tothree clock pulses of output clock cycle AT, with respect to input clockpulses.

For starting value R, for instance, a register value, stored in aregister in a user, particularly in the controller, any number of valuesis possible. If R is drawn from a register, a starting value of 0 isavailable, since it is easily achievable in the register by a reset,particularly a power-on reset, and no further adjustment is necessary.The only prerequisite with respect to the values E and A is that E≧A, inother words, the numerator of time unit ratio TUR is greater than thedenominator, which means that from a faster input clock cycle a sloweroutput clock cycle is formed. Other than that, E and A may be selectedat will.

In one embodiment, the exemplary method according to the presentinvention is extended to the extent that a scaling of the clock pulsesof output clock cycle AT is achieved. The number of clock pulses ofinput clock cycle E and the number of clock pulses of output clock cycleA are again integers, although this time having a time unit ratioTUR=E/A≧2  (equation 10)and F as an integer, with F≦time unit ratio TUR(F≦TUR). Besidesintermediate value R, an additional intermediate value, a scalingintermediate value T is introduced, which is an integer just as R is,and in this example also starts at 0.

FIG. 4 shows the extension of the exemplary method according to thepresent invention. The method starts in block 300. In block 301,comparably as in FIG. 2, the clock pulses of input clock cycle ET areevaluated, at each input clock pulse the following process being run. Inquery 302 a check is made as to whetherR>E−A*F  (equation 11)holds. If this is not satisfied, this yields a truth value FALSE, thesystem reaches block 303, where R is again adjusted, and this accordingtoR:=R+A*F  (equation 12).

However, if the condition according to equation 11 in block 302 issatisfied, this then yields a truth value TRUE, and the system reachesblock 304. In that block, on the one hand, in block 305 intermediatevalue R is adjusted according to:R:=R+A*F−E  (equation 13)

At the same time, or, as will be described later in a variant, offset toit, in block 306 a scaled clock pulse, that is, a clock pulse of ascaled clock cycle TT is now generated, comparably to the clock pulse ofoutput clock cycle AT of the previous example. Consequently, up to thispoint, the extension corresponds to the aforesaid example, F beingselected=1 in the previously described example. But now scaledintermediate value T is checked in block 309, in fact according to theconditionT<F  (equation 14)

Corresponding to this condition, this now yields an additional truthvalue TRUEZ or FALSEZ. If the condition T<F is satisfied, truth valueTRUEZ comes about, and the system reaches block 310, where T isincremented, that is,T:=T+1  (equation 15)

If the condition T<F in block 309 according to equation 14 is notsatisfied, this then yields a truth value FALSEZ, and the system reachesblock 311. Here, on the one hand, in block 312 partial intermediatevalue T is reset, that is,T:=0  (equation 16)and, on the other hand, in block 313 a clock pulse of a third clockcycle of output scaled clock cycle ATT is generated.

This now may occur as in block 304 or in the preceding example too,essentially simultaneously, or offset in time.

From block 303, 310 and 311 the system now comes to query 307, where itis only checked whether the method should be maintained further or is tobe maintained. If yes, the system again reaches block 301, where thenext clock pulse of the input clock cycle is evaluated. If the method isended, for example, according to a time condition or because, over aspecifiable time period no clock pulses of input clock cycle ET weredetected, etc, the system reaches block 308, the end of the method. Heretoo, the termination condition is optional.

Consequently, in accordance with the method described above, a scaledpulse of scaled timing TT, that is, of the second clock cycle here inthis exemplary embodiment, is generated in accordance with block 304 and306, and in fact for each clock pulse of input clock cycle ET, for whichthe condition according to equation 11 (R>E−A*F) is satisfied.

Equally, a clock pulse of an output clock cycle, here the clock pulse ofthe third clock cycle, of the output scaled clock cycle ATT, accordingto block 311, especially 313, is generated for each clock pulse ofscaled clock cycle TT for which scaled intermediate value T assumes acertain value. This value may be selected or specified, and may be 0,for example. That is, the clock pulse of output scaled clock cycle ATTis generated for each clock pulse of scaled clock cycle TT, for example,when T changes from F−1 to 0.

In one special specific embodiment, F may be limited to values of 2^(n),where nεN, so that the multiplication A*F may be replaced by a shiftingof A by n bits (to the left or right, depending on system conditions).Here too, there are comparable algorithms, and the more general schememay be described as follows:

-   -   During the application, there is a process which runs once at        each clock pulse of input clock cycle ET. This is evaluated in        the example in block 301.    -   This process is able to generate a clock pulse for a scaled        pulse TT for the subdivisions and possibly also clock pulses for        the full output clock cycle, here as output scaled pulse ATT.    -   Scaled clock pulse TTP, or the clock pulse of scaled clock cycle        TT is generated when the comparison of an intermediate variable        or the intermediate variable R with a fixed value C which is        simple to calculate from E and A, particularly also in hardware,        yields a certain truth value TRUE or FALSE. In the example, this        occurs corresponding to query 302 and block 304.    -   If a scaled clock pulse TTP, that is, a clock pulse of scaled        clock cycle TT, is generated, again a certain manipulation, here        a third manipulation M3 is undertaken with intermediate value R,        such as was done before with addition and subtraction of a value        calculable from A and E, according to block 305.    -   The clock pulse of output scaled timing ATT may be generated if        the comparison of a further intermediate variable or the scaled        intermediate value T having a fixed scaled value TC yields an        additional truth value TRUEZ or FALSEZ. In this context, scaled        intermediate value T is able to count, for example, scaled clock        pulse TTP, that is, the clock pulses of scaled clock cycle TT.    -   If a clock pulse of output scaled clock cycle ATT is generated,        a further, specifiable manipulation M4 is undertaken with T,        corresponding to block 312.    -   If no scaled clock pulse TTP is generated, that is, no clock        pulse of scaled clock cycle TT or no clock pulse of output        scaled clock cycle ATT, a specifiable additional manipulation M5        is undertaken with R according to block 303, or with T a further        specifiable manipulation M6 is undertaken according to block 310

Consequently, in this example, the scaled clock cycle corresponds to theclock cycle denoted as output clock cycle in the previous example, whichin both cases corresponds to the second clock cycle, when input clockcycle ET is assumed to be the first clock cycle. Thus, in addition thepossibility arises here of generating an additional third clock cyclebased on the second timing, that is, the scaled clock cycle, namelyoutput scaled clock cycle ATT.

As in the previously named example, here too the corresponding variantsare possible, as has been described already in connection with FIG. 2.Thus, this means here too, that the clock cycle output either of thescaled clock cycle or the output scaled clock cycle and the change ofintermediate value R or scaled intermediate value T may occur, on theone hand, essentially simultaneously or, on the other hand, in an offsetmanner, particularly offset by clock pulses of the first clock cycle ofinput clock cycle ET. The same applies to the additional variant thatthe scaled clock cycle or the output partial timing is always generated,and only the difference with respect to R or T is additionally set.

The continuation according to FIG. 4 will now be explained once more ingreater detail in FIG. 5, in a concrete example. The number of inputclock cycles E is again 7, and the number of output clock cycles A isagain 3, F=2 being selected. This yields E−A*F=1. R and T, in thisexample, begin at 0. This, again, has the advantage that the values maybe written into memories or registers, and when there is a reset,especially a power-on reset, that is, especially after a voltageinterruption, the starting values of R and T are present. In the firstinput clock pulse, R starts at 0, and then the system goes to block 303,and according to equation 12, R=6 is determined for the next clockpulse. At the next run-through, at the next clock pulse, consequentlyR=6, that is, it is greater than 1. The system reaches block 304, wherea scaled clock pulse is generated. At the same time, T continues as 0,and the system reaches block 310, where T is incremented.

Consequently, at the next input clock pulse at T2, R=5>1. The systemagain reaches block 304 where R is calculated anew to R=4, a scaledclock pulse TT is generated, and since T is still less than 2, thisvalue of T is incremented anew in block 310.

At T=3, the next input clock pulse, consequently R=4 is still greaterthan 1, and the system reaches block 304. Thereby the next value for Ris calculated, R=3, and a scaled clock pulse TT is generated. Now block309 delivers the truth value FALSEZ, since T=2, which means that T isset to 0 in block 312, and an output scaled clock pulse ATT is generatedin block 313. At T=4, R at 3 is still greater than 1. Thus, in block 304a scaled clock pulse TTP is generated anew, and the next R value iscalculated as R=2.

In query 309, T at 0 is less than 2, and is incremented in block 310 toT=1.

At point T5 at the next input clock pulse, consequently, R=2>1. Thus, ascaled clock pulse is generated in block 304, and the next value R=1 iscalculated. In block 309, T=1<2 gives truth value TRUEZ, and the systemreaches block 310, where T as 1<2 is incremented to 2.

At T6 R=1. Consequently, query 302 yields truth value FALSE, and inblock 303 R is calculated to be 7 according to equation 12.

At the next input clock pulse at T7, R=7>1. Thus, in block 304 a scaledclock pulse is generated, and at the same time R is calculated to be 6.In block 309 T=2 yields truth value FALSEZ, and the system reaches block311. Here, T is set to 0 again in block 312, and in block 313 an outputscaled clock pulse ATT is generated.

At T8 the values at T1 are reached again, and the run repeats itself andbegins over again.

This shows a method as well as a device, a bus system and a user of thebus system in which the method is able to be carried out, namely inhardware or in software, in order to implement a fractional rationaltime unit ratio in a simple manner.

The use of the scaler method according to the present invention, forinstance in an IC, among other things may be shown on the one hand viathe data specification of the IC (the scaler ratio is set as thequotient of two integers) and/or on the other hand by measuring theinput clock cycle and the output clock cycle, or rather the functions ofthe IC controlled by the output clock cycle. In this context, the inputclock cycle ET is the first clock cycle from which one starts. From thisa second clock cycle is generated, which, in the first example is simplydetermined using output clock cycle AT and in the second example usingscaled clock cycle TT, in the third example, an additional clock cycle,the output scaled clock cycle ATT is output as third clock cycleadditionally to, or instead of the second clock cycle, of scaled clockcycle TT.

1. A method for forming second clock pulses of a second clock cycle fromfirst clock pulses of a specified first clock cycle in a bus systemhaving at least one user, the method comprising: determining orspecifying a first number of the first clock pulses of the first clockcycle in a specifiable time interval; determining or specifying a secondnumber of the second clock pulses of the second clock cycle in thespecifiable time interval; specifying an intermediate value of thenumber of clock pulses in the specifiable time interval; comparing theintermediate value to a value which is formed from the first number ofthe first clock pulse and the second number of the second clock pulses,the comparing yielding a truth value of true or false; and generating aclock pulse of the second clock cycle as a function of the truth value;wherein, besides the intermediate value, a scaled intermediate value isspecified which is compared to a specifiable scaled value, and, bycomparing to the scaled value an additional truth value of true or falseis yielded, a clock pulse of a third clock cycle being generated fromthe clock pulse of the second clock cycle as a function of theadditional truth value.
 2. The method of claim 1, wherein the steps arerun off once as a function of each clock pulse of the first clock cycle.3. The method of claim 1, wherein the intermediate value is changeddifferently, as a function of the comparing and thus as a function ofthe truth value.
 4. The method of claim 3, wherein the generation of theclock pulse of the second clock cycle and the change of the intermediatevalue by a specifiable number of the first clock pulses of the firstclock cycle is performed in an offset manner.
 5. The method of claim 1,wherein the value to which the intermediate value is compared is yieldedby the relation of C=E−A*F, F being an integer.
 6. The method of claim1, wherein a clock pulse of the second clock cycle is generated for eachclock pulse of the first clock cycle when the condition of R>E−A*F issatisfied, F being an integer.
 7. The method of claim 5, wherein theinteger F is limited to values of 2^(n) where n 0 N, and themultiplication A*F is replaced by a shifting of the binary value of A byn bits.
 8. The method of claim 1, wherein during generation of thirdclock pulses of the third clock cycle, the second clock pulses of thesecond clock cycle are available only in the user, but are not output byit.
 9. The method of claim 1, wherein the scaled intermediate value isdifferently changed as a function of the comparing to the scaled value,and thus as a function of the additional truth value.
 10. The method ofclaim 9, wherein generation of third clock pulses of a third clock cycleand the change of the scaled intermediate value by a specifiable numberof the first or second clock pulses of the first clock cycle or thesecond clock cycle is performed in an offset manner.
 11. A device in abus system for forming second clock pulses of a second clock cycle fromfirst clock pulses of a specified first clock cycle in a bus systemhaving at least one user, the device comprising: a first determiningarrangement to determine or specify a first number of the first clockpulses of the first clock cycle in a specifiable time interval; a seconddetermining arrangement to determine or specify a second number of thesecond clock pulses of the second clock cycle in the specifiable timeinterval; a specifying arrangement to specify an intermediate value ofthe number of clock pulses in the specifiable time interval; a comparingarrangement to compare the intermediate value to a value which is formedfrom the first number of the first clock pulses and the second number ofthe second clock pulses, the comparing yielding a truth value of true orfalse; and a generating arrangement to generate a clock pulse of thesecond clock cycle as a function of the truth value; wherein, besidesthe intermediate value, a scaled intermediate value is specified whichis compared to a specifiable scaled value, and, by comparing to thescaled value an additional truth value of true or false is yielded, aclock pulse of a third clock cycle being generated from the clock pulseof the second clock cycle as a function of the additional truth value.12. A bus system comprising: at least one user having a device forforming second clock pulses of a second clock cycle from first clockpulses of a specified first clock cycle in the bus system, the bussystem having at least one user, the device including: a firstdetermining arrangement to determine or specify a first number of thefirst clock pulses of the first clock cycle in a specifiable timeinterval; a second determining arrangement to determine or specify asecond number of the second clock pulses of the second clock cycle inthe specifiable time interval; a specifying arrangement to specify anintermediate value of the number of clock pulses in the specifiable timeinterval; a comparing arrangement to compare the intermediate value to avalue which is formed from the first number of the first clock pulsesand the second number of the second clock pulses, the comparing yieldinga truth value of true or false; and a generating arrangement to generatea clock pulse of the second clock cycle as a function of the truthvalue; wherein, besides the intermediate value, a scaled intermediatevalue is specified which is compared to a specifiable scaled value, and,by comparing to the scaled value an additional truth value of true orfalse is yielded, a clock pulse of a third clock cycle being generatedfrom the clock pulse of the second clock cycle as a function of theadditional truth value.
 13. A user in a bus system, comprising: a devicefor forming second clock pulses of a second clock cycle from first clockpulses of a specified first clock cycle in the bus system, the deviceincluding: a first determining arrangement to determine or specify afirst number of the first clock pulses of the first clock cycle in aspecifiable time interval; a second determining arrangement to determineor specify a second number of the second clock pulses of the secondclock cycle in the specifiable time interval; a specifying arrangementto specify an intermediate value of the number of clock pulses in thespecifiable time interval; a comparing arrangement to compare theintermediate value to a value which is formed from the first number ofthe first clock pulses and the second number of the second clock pulses,the comparing yielding a truth value of true or false; and a generatingarrangement to generate a clock pulse of the second clock cycle as afunction of the truth value; wherein, besides the intermediate value, ascaled intermediate value is specified which is compared to aspecifiable scaled value, and, by comparing to the scaled value anadditional truth value of true or false is yielded, a clock pulse of athird clock cycle being generated from the clock pulse of the secondclock cycle as a function of the additional truth value.